Other articles

  1. SystemVerilog Rant

    I dislike SystemVerilog.

    The only thing I dislike more than SystemVerilog itself is that it is really the only choice for a hardware description language today. Nowadays there are two alternative, both horrible: VHDL, and SystemC. VHDL is a non-starter (it's based on Ada), and SystemC isn't even ...

    read more

    There are comments.

Page 1 / 1